[Blabber] Free FPGA / Intel Stuff
jamescarpino at yahoo.com
Sun May 7 07:53:43 UTC 2017
Joshua & JC: I'll see if I can make it in on Tuesday to talk about FPGA.
I tinkered with a 6502/C64 and a few other things on an FPGA, but my FPGA was bigger than the Mojo's... 500k gates vs. something less on the Mojo (not sure, I looked it up before, it's probably more like 50K-100K). (John correct me please if that's off.) The one I used was this,http://store.digilentinc.com/spartan-3e-starter-board-limited-time/
and I'm not pushing it. I came to believe that the IDE from Altera runs smoother than Xilinx's, not that I spent much time on it... and those are the two biggest companies. Oh and I'm not saying don't take John's suggestion wrt. Lattice, I am not knowledgeable on the matter, but it sounds good to be free of the shackles of the closed-source IDE's from the big two. Also when I was looking around I liked the Altera eval/education boards better, but I had already bought Xilinx boards. (My Xilinx Digilent board had 3-bit VGA instead of ANYTHING normal. That meant only 8 colors!! For VGA? haha they saved two cents on a bunch of resistors.)
Overview of the market, super abbreviated:
When I dove into FPGA, it took me months to understand what I was doing and it was very painful. As Chris suggested, the synthesize times are ridiculous even for modest projects. Small ok, but medium is bad. So for example, if you want to put a CPU on your FPGA, and you want to put a virtual ROM in the FPGA, unless you manage to put that ROM externally somehow or create a bootloader of sorts, each time you change code you'd have to re-synthesize the whole project, which can take many minutes depending on the complexity (and your computer). Setting aside the challenge of learning & thinking differently, the most aggravating part was the development time. Once your project outgrows the simulator, it becomes an all-out war to plan adequate debugging into your project so that you don't waste time at each cycle. I think we're spoiled by the modern compiling era. And FPGA projects don't partial-compile so easily (and in Xilinx you can't do partitioned builds unless you pay extra).
On the plus side, you can do almost anything, in your efforts to solve whatever problems. So for instance if you incorporate a processor, you could literally put a set of LED's straight onto an accumulator, and bring out a button to single-step it. You can make dual-port RAM, and put multiple CPUs into one FPGA depending how big it is. (You could put in an extra CPU to debug the first one, if you are swift. You can even build a logic analyzer or a memory debugger within the FPGA.)
Some CPU architectures are intended to be put into the FPGA and they are more economical on FPGA resources than the "real world" CPUs; I haven't gotten into those yet, probably because it means learning yet another compiler/assembler toolchain. But still, very cool and I'll try them eventually.
This has reawakened my FPGA brain and I'm getting a lot of new ideas.
From: Connor Connor <john.theman.connor at gmail.com>
To: Hack Manhattan! <blabber at list.hackmanhattan.com>
Sent: Saturday, May 6, 2017 9:33 PM
Subject: Re: [Blabber] Free FPGA / Intel Stuff
Vincent: I will put at least one Galileo in the fixers collective box
during this Tuesday's open house.
Joshua: There are a lot of tutorials for the Mojo:
https://embeddedmicro.com/tutorials/mojo/ so it may be slightly easier
to learn than other systems. But the hottest thing in the FPGA world
right now is the Lattice iCEstick: http://www.latticesemi.com/icestick
since it is the only FPGA with a free software toolchain. (Although
strictly speaking, the spartan 6 is significantly more powerful.)
Everything is an uphill battle, but if you want to do processor stuff
with an FPGA, hit me up at an open-house and we can rap about it. (I
don't know much about more general purpose FPGA uses, but some other
On Sat, May 6, 2017 at 7:10 PM, Chris Stratton <cs07024 at gmail.com> wrote:
> Looks like it has a Xilinx spartan 6 on it. No worse than any other,
> tools perhaps slightly less picky about beginner mistakes than a few.
> Given compilation times very much worth validating designs in simulation.
> Make sure things gets reset somehow to start (may be more automatic
> with this than with some)
> Set I/O constraints or settings or whatever.
> Watch I/O voltages.
> On Sat, May 6, 2017 at 6:52 PM, Joshua Grebler <jgreb314 at gmail.com> wrote:
>> How's that FPGA for learning? Or would it be an uphill battle?
>> On May 6, 2017 1:48 PM, "Connor Connor" <john.theman.connor at gmail.com>
>>> I am doing some spring cleaning. Does anyone want a MOJO V3 FPGA and
>>> two Intel Galileos? I can bring them to the space on Tuesday if
>>> anyone wants them. I think I also have a few Intel Edisons floating
>>> around too if anyone is interested (but I can't seem to find them, so
>>> no promises.)
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